1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a substrate potential detection circuit generating a substrate potential which is a negative voltage in the semiconductor device.
2. Description of the Background Art
FIG. 10 is a block diagram showing a configuration of a conventional semiconductor device which includes a substrate potential detection circuit 502.
Referring to FIG. 10, a functional circuit 500 included in the semiconductor device requires a substrate potential VBB which is a negative voltage, and must generate a negative voltage internally if no negative voltage is supplied from the outside of the semiconductor device. Therefore, the semiconductor device includes a negative potential generation circuit 504 outputting substrate potential VBB which is a negative voltage, and a substrate potential detection circuit 502 receiving substrate potential VBB, determining whether or not a generated potential is appropriate, and controlling negative potential generation circuit 504. A charge pump circuit or the like is employed as negative potential generation circuit 504.
FIG. 11 is a circuit diagram showing a first configuration example of substrate potential detection circuit 502 shown in FIG. 10.
Referring to FIG. 11, substrate potential detection circuit 502 includes an intermediate potential generation circuit 572 receiving substrate potential VBB and outputting a divided potential which is an intermediate potential between a power supply potential VDD and a ground potential, and an inverter 574 receiving the output of intermediate potential generation circuit 572, determining whether the output is higher or lower than an inversion threshold value, and outputting a control signal /EN.
Intermediate potential generation circuit 572 includes a P-channel MOS transistor 576 having a source and a back gate coupled to power supply potential VDD, a drain connected to a node N50 and a gate connected to a ground node, and a P-channel MOS transistor 578 having a source and a back gate connected to node N50, a drain connected to a ground node and a gate receiving substrate potential VBB. A divided potential, which is an intermediate potential between power supply potential VDD and the ground potential, is outputted from node N50.
Inverter 574 includes a P-channel MOS transistor 580 having a source and a back gate coupled to power supply potential VDD, a drain connected to a node N51 and a gate connected to node N50, and a N-channel MOS transistor 582 which is connected between node N51 and a ground node and which has a gate connected to node N50. Control signal /EN is outputted from node N51.
FIG. 12 shows the relationship between substrate potential VBB inputted into intermediate potential generation circuit 572 and the divided potential outputted from node N50.
Referring to FIGS. 11 and 12, if P-channel MOS transistors 576 and 578 have the same electrical characteristic and the following relationship is satisfied, the bias conditions of P-channel MOS transistors 576 and 578 become equal to each other:
VBB=xe2x88x92(xc2xd)xc3x97VDD.
If the bias conditions of P-channel MOS transistors 576 and 578 become equal to each other, the power supply voltage is divided by these transistors into two. Then, the divided potential outputted from node N50 becomes (xc2xd)xc3x97VDD.
Further, if the following relationship is satisfied, the divided potential is lower than (xc2xd)xc3x97VDD:
VBB less than xe2x88x92(xc2xd)xc3x97VDD.
On the other hand, if the following relationship is satisfied, the divided potential is higher than (xc2xd)xc3x97VDD:
VBB greater than xe2x88x92(xc2xd)xc3x97VDD.
FIG. 13 shows the input/output characteristics of inverter 574 shown in FIG. 11.
Referring to FIGS. 11 and 13, inverter 574 outputs xe2x80x9cHxe2x80x9d logic if an input voltage is lower than a logic threshold value, and outputs xe2x80x9cLxe2x80x9d logic if the input voltage is higher than the logic threshold value.
The logic threshold value of inverter 574 is set at (xc2xd)xc3x97VDD. Then, substrate potential detection circuit 502 outputs xe2x80x9cHxe2x80x9d if the following relationship is satisfied:
VBB less than xe2x88x92(xc2xd)xc3x97VDD.
On the other hand, substrate potential detection circuit 502 outputs xe2x80x9cLxe2x80x9d if the following relationship is satisfied:
VBB greater than xe2x88x92(xc2xd)xc3x97VDD.
That is, by setting the electrical characteristics of P-channel MOS transistors 576 and 578 equal to each other and selecting (xc2xd)xc3x97VDD as the logic threshold value of inverter 574, substrate potential detection circuit 502 changes an output at a point at which inputted substrate potential VBB coincides with xe2x88x92(xc2xd)xc3x97VDD. The potential at this point will be referred to as detected potential.
There is a case where a potential other than xe2x88x92(xc2xd)xc3x97VDD is to be set as the detected potential in the conventional substrate potential detection circuit shown in FIG. 11. In this case, two methods may be considered. First, if substrate potential VBB becomes a desired value by intentionally setting the electrical characteristic of P-channel MOS transistor 576 and that of P-channel MOS transistor 578 different from each other, a divided potential outputted from node N50 is made equal to (xc2xd)xc3x97VDD. Second, the logic threshold value of inverter 574 is changed from (xc2xd)xc3x97VDD.
To set the electrical characteristic of P-channel MOS transistor 576 and that of P-channel MOS transistor 578 different from each other, such measures as to change the threshold voltage Vth of the P-channel MOS transistors or the resistance value of the channel parts thereof may be taken. However, if the electrical characteristics of transistors are changed by a change in manufacturing conditions or the like, the electrical characteristics of transistors cannot be set different from each other as desired and a desired divided potential cannot be obtained.
Moreover, if the logic threshold value of inverter 574 is changed, the following disadvantage arises. The logic threshold value of an inverter is determined according to the characteristics of both a pull-up element and a pull-down element. Due to this, in a complementary (CMOS) semiconductor device constituted so that a pull-up side is formed by a P-channel MOS transistor and a pull-down side is formed by an N-channel MOS transistor, if the complementary characteristics of the P-channel MOS transistor and the N-channel MOS transistor are changed by a change in manufacturing conditions or the like, a desired logic threshold cannot be obtained.
Under these two circumstances, the conventional art shown in FIG. 11 has a disadvantage in that a desired detected voltage cannot be stably obtained if an arbitrary potential is selected as a substrate potential.
FIG. 14 is a circuit diagram showing a configuration of a substrate potential detection circuit 502a as a second configuration example.
Referring to FIG. 14, substrate potential detection circuit 502a includes a voltage determination circuit 574a in place of inverter 574 in the configuration of substrate potential detection circuit 502 shown in FIG. 11.
Voltage determination circuit 574a includes a reference potential output circuit 586 outputting a reference potential which is a half of power supply potential VDD, and a comparison circuit 588 comparing the output of reference potential output circuit 586 with that of intermediate potential generation circuit 571 and outputting a control signal EN.
Reference potential output circuit 586 includes a P-channel MOS transistor 590 having a source and a back gate connected to power supply potential VDD and a drain and a gate connected to a node N52, and a P-channel MOS transistor 592 having a source and a back gate connected to node N52 and a gate and a drain connected to a ground node. The positive input node of comparison circuit 588 is connected to node N50 and the negative input node of comparison circuit 588 is connected to node N52.
FIG. 15 shows the input/output characteristics of comparison circuit 588.
Referring to FIGS. 14 and 15, comparison circuit 588 amplifies the difference between a potential applied to the positive input node and a potential applied to the negative input node, and outputs the amplified potential difference. The potential applied to the negative input node acts as the logic threshold value of inverter 574 in the conventional art shown in FIG. 11.
The potential inputted into the negative input node is (xc2xd)xc3x97VDD. If the potential inputted into the positive input node is lower than (xc2xd)xc3x97VDD, comparison circuit 588 outputs xe2x80x9cLxe2x80x9d logic. On the other hand, if the potential inputted into the positive input node is higher than (xc2xd)xc3x97VDD, comparison circuit 588 outputs xe2x80x9cHxe2x80x9d logic.
That is, substrate potential detection circuit 502a outputs xe2x80x9cLxe2x80x9d logic if the following relationship is satisfied:
VBB less than xe2x88x92(xc2xd)xc3x97VDD.
Substrate potential detection circuit 502a outputs xe2x80x9cHxe2x80x9d logic if the following relationship is satisfied:
VBB greater than xe2x88x92(xc2xd)xc3x97VDD.
In other words, the detected potential of substrate potential detection circuit 502a is xe2x88x92(xc2xd)xc3x97VDD.
If a substrate potential other than xe2x88x92(xc2xd)xc3x97VDD is to be detected using substrate potential detection circuit 502a, the problem of the adjustment of the logic threshold value of the inverter that arises to substrate potential detection circuit 502 does not generate. This is because a logic determination is made based on the potential which is applied to the negative input node of comparison circuit 588 and which generates analogically.
Nevertheless, the disadvantage which arises to intermediate potential generation circuit 572 because a divided potential other than (xc2xd)xc3x97VDD is obtained, remains unsolved as in the case of the circuit shown in FIG. 11. That is, if the electrical characteristics of transistors are changed by a change in manufacturing conditions or the like, a desired divided potential cannot be obtained.
An object of the present invention is to provide a semiconductor device capable of stably detecting a desired substrate potential if the substrate potential other than xe2x88x92(xc2xd)xc3x97VDD is detected.
In short, the present invention provides a semiconductor device internally generating a negative substrate potential, including a first reference potential generation circuit, an intermediate potential generation circuit, a determination circuit and a negative potential generation circuit.
The first reference potential generation circuit generates a first reference potential higher than a target potential of the substrate potential by a half of a potential difference between a power supply potential and a ground potential. The intermediate potential generation circuit receives the substrate potential, and outputs a divided potential which is an intermediate potential between the power supply potential and the ground potential.
The intermediate potential generation circuit includes first and second P-channel MOS transistors. The first P-channel MOS transistor has a source coupled to the power supply potential, a gate receiving the reference potential, and a drain outputting the intermediate potential. The second P-channel MOS transistor is connected between the drain of the first P-channel MOS transistor and a ground node applied with the ground potential, and has a gate receiving the substrate potential.
The determination circuit receives the intermediate potential, and determines whether the substrate potential is higher or lower than the target potential. The negative potential generation circuit drives the substrate potential in a negative potential direction in accordance with an output of the determination circuit.
According to another aspect of the present invention, a semiconductor device internally generating a negative substrate potential, includes an intermediate potential generation circuit, a determination circuit, and a negative potential generation circuit.
The intermediate potential generation circuit receives the substrate potential, and outputs an intermediate potential between a power supply potential and a ground potential.
The intermediate potential generation circuit includes first to third P-channel MOS transistors.
The first P-channel MOS transistor has a source connected to a power supply node applied with the power supply potential, and a drain outputting the intermediate potential. The second P-channel MOS transistor has a source connected to the drain of the first P-channel MOS transistor, a gate connected to a ground node applied with the ground potential, and a drain connected to a gate of the first P-channel MOS transistor. The third P-channel MOS transistor is connected between the drain of the second P-channel MOS transistor and the ground node, and has a gate receiving the substrate potential.
The determination circuit receives the intermediate potential, and determines whether the substrate potential is higher or lower than a target potential of the substrate potential. The negative potential generation circuit drives the substrate potential in a negative potential direction in accordance with an output of the determination circuit.
Therefore, a main advantage of the present invention is as follows: the semiconductor device is less influenced by a change in manufacturing conditions and a target substrate potential can be arbitrarily selected.
Another advantage of the present invention is as follows: the semiconductor device is less influenced by a change in manufacturing conditions and xe2x88x92(⅓) times as high as a power supply potential can be selected as a target substrate potential while suppressing a circuit size to be small.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.